The present invention relates to a system for simultaneously interfacing with and debugging multiple processor cores on an integrated circuit device.
System-on-a-Chip (SoC) refers to integrated circuits that are generally custom made for a specific application and contain at least one processor core, memory, and/or peripheral devices. A processor core provides computational capabilities through fetched program and data memory accesses. For purposes of this specification, the term “processor core” refers to devices including, but not limited to a CPU (central processing unit), Core, CPU Core, Core Device, IP (intellectual property) cores, JTAG UART, logic analyzer cores, microprocessors, and/or any mechanism suitable for testing, validating, and/or debugging. An SoC device may include multiple processor cores. Some SoC devices are homogeneous (having identical processor cores); others are heterogeneous (having different processor cores).
Developing an SoC device is a multi-step process. Early design steps are generally done virtually on paper or on a computer. These virtual designs are often referred to as pre-silicon models. The pre-silicon model may be, for example, designed, developed, tested, debugged, and validated on an engineering workstation with synthesis and simulation tools. Then, a first silicon device is created. The first silicon device may be a field programmable gate array (FPGA) or a first run application-specific integrated circuit (ASIC) (generally smaller than a full run) of what is expected to become the final embodiment of the SoC device. The first silicon device may include enhancements for software and hardware debugging. The first silicon device is then tested, debugged, and validated. If these tests are successful, the SoC device may be mass-produced.
On-chip debug capability is rapidly becoming the method-of-choice for developing and integrating SoC device application code. More recently, the process of on-chip debugging aids pre-silicon hardware-based simulation and first silicon debug and validation. With the explosive growth in SoC designs and new processor cores, more features and functions are being integrated into the silicon. At the same time, processor speeds are increasing rapidly and time-to-market pressures are greater than ever. Further, design constraints make it difficult for traditional debug tools to interface and work properly in SoC designs.
Joint Test Access Group (JTAG) is a set of standard signals and a protocol (IEEE Standard 1149.1) used to communicate to a device. The JTAG source is the master and the chip it is communicating with is a slave. JTAG provides a means of sending data to the device and reading data back from the device. JTAG is a real-time protocol. As such, it requires a probe (e.g. a JTAG master) that must simultaneously transmit and receive data. The JTAG protocol does not provide means for waiting. For example, a slave device cannot request a master device to wait for access.
A fundamental requirement of any debug system for SoC devices is integration with off-the-shelf probes and software. Typically, off-the-shelf debug probes use the standard JTAG protocol but not a standardized physical connector and, therefore, cannot share the connector with other off-the-shelf probes. A few standardized JTAG-software devices exist, such as JTAG Servers, but these require modifications to the debug software on the off-the-shelf probes.
One attempt to address the ever-changing demands of on-chip testing and debugging utilizes a traditional in-circuit emulator (ICE) that connects to numerous device pins including address, data, and control signals. This solution is problematic because it is practically impossible to actively manipulate and interface to an SoC device due to the SoC's limited quantity of pins and limited access of the control and status signals that traditional ICEs require.
Another attempt to test and debug SoC integrations uses a modified ICE device. The modifications include a component called a “bond-out” or “test” chip. These modified ICE devices “bond out” or wire from the chip die all the required debug signals to external pins. This approach is no longer practical because of the difficulty of maintaining two-versions of the rapidly evolving SoC designs and the limitation of package pins.
Logic analyzers are ineffective tools for testing and debugging in the SoC environment because, in many instances, signals for tracing are not available at the processor pins. In some cases, all the debug logic is on-chip, including processor and/or bus trace and triggering. Further, for SoCs with external trace ports, to properly trace and view the trace results, the traditional logic analyzer must first be customized and configured to interface with the specific SoC device. As a result of this customization, overall product development cycle times and costs increase undesirably.
Existing test and measurement instruments inadequately address design flexibility needs for multiple core debug and test. For example, SoC device designers need design flexibility to incorporate multiple homogeneous and/or heterogeneous processor cores from various third-party sources. These processor cores, for instance, can include a Reduced Instruction Set CPUs (RISC) processor, a Digital Signal Processor (DSP), on-chip instrumentation blocks for bus-trace, triggering, and performance-analysis. For most cases, each of the processor cores uses a standardized JTAG interface-port for control and debug purposes including, for example, start-stop execution, program download, memory and register access, and hardware breakpoint programming. For example, on OCI® brand on-chip instrumentation blocks, the JTAG port is used to program trigger-conditions, acquisition modes, monitor operating state, retrieve trace data, and retrieve measurement data.
Inaccessibility of the control and bus signals plagues many current SoC device designs. The lack of the physical pins on these highly integrated chips often blocks access for traditional off-chip instrumentation, such as debug probes. This creates great difficulty in verifying the operation of first silicon devices and creates many hardware and software integration roadblocks that adversely affect the time-to-market.
One traditional solution for debugging multiple processor cores on an SoC device is to include one physical Joint Test Access Group (JTAG) port on integrated circuit (IC) for each on-chip controllable processor core. If each processor core requires its own JTAG port at the edge of the chip, then physical pin requirements would consume package real estate, making multi-processor core SoC devices impractical. A lack of silicon area for the logic and memory blocks, typically, is not the most significant impediment to SoC debugging. Rather, the most significant impediment to SoC debugging is a lack of pins. For example, a multi-processor core SoC device with dedicated and separate JTAG ports for each processor core would require a corresponding set of five JTAG pins and a dedicated pin for break input and another dedicated pin for go-halt status. Dedicating five pins per processor core wastes pins as a resource. Consequently, each processor core cannot accommodate a dedicated JTAG port.
Sharing access to a common external JTAG port is another traditional solution for test, debug, and validation of multiple-processor core SoC devices. For example, multiple debugging devices share the access to multiple on-chip processor cores by daisy chaining each processor core, allowing them to be addressed individually. This solution is problematic because each of the multiple debugging devices, such as commercially available JTAG-enabled probes (test instruments), supports only one specific device, and is, therefore, unable to interact with any of the other multiple processor cores in the chain. Because two individual JTAG debug probes cannot operate simultaneously on the common shared JTAG connection, only one probe could be connected at one time; therefore, only one processor core may be debugged at a time.
One attempt to address port sharing for testing integrated circuits is described in U.S. Pat. No. 6,584,590 (the “Bean reference”) entitled “JTAG PORT-SHARING DEVICE.” The Bean reference specifies a port-sharing probe that switches multiple JTAG inputs to one JTAG port on the integrated circuit under test. The Bean reference describes a system in which only one probe at a time may access this common JTAG connection, thus limiting debug to only one processor core at a time. This, in turn, prevents simultaneous debugging of multiple processor cores and their hardware and software interactions.